Controlled-Root Formulation for Digital Phase-Locked Loops
نویسندگان
چکیده
Previous analyses (e.g., [1, 2]) of digital phase-locked loops (DPLLs) are based on the traditions of analog loops and introduce analog considerations, such as loop-filter time constants and uncompensated gain variations, that are unnecessary for “fully digital” loops. This reliance on analog tradition makes digital-loop analysis unnecessarily cumbersome and impedes the progress of analysts with little analog training. Theory for digital loops can be developed from first principles without reference to analog concepts. With an appropriately formulated, fully digital analysis, one discovers that DPLL theory and design become more straightforward and understandable (particularly for thirdand fourth-order loops) and that loop performance is more easily controlled for “high-gain” loops. In the new formulation, loop-filter constants are determined from loop roots that can be selectively placed in the s-plane in pairwise fashion on the basis of a new set of independent parameters, where each parameter has a simple and direct physical meaning in terms of loop noise bandwidth, root-specific decay rate, or root-specific damping. For example, a simple choice of parameter values will automatically give a loop a selected loop bandwidth and supercritically damped behavior (i.e., all roots real, negative, and equal). Thus, the need to solve for root location as a function of traditional loop parameters (e.g., BL, r, and k for a third-order loop [2]) is eliminated and analysis is simplified. The new parameterization is made feasible in a practical sense by the fact that digital loops can often be designed so that they do not suffer significantly from the effects of amplitude variations. That is, variations in signal amplitude, due to either gain instability or signal-power changes, can often be accounted for by using a normalized phase extractor [3]. In this case, a fully digital DPLL does not require the analysis or precautions [e.g., 2] necessitated in other DPLL designs by potential amplitude variations. Even when amplitude variations cannot be removed, the new formulation can be used to generate a reference or target configuration whose response can then be tested with respect to amplitude variations. Previous analyses (e.g., [1, 2]) of discrete-update (DU) loops have started with the closed-loop equation in the “continuous-update” (CU) limit in which BLT! 0, where BL is the loop noise bandwidth and T is the loop update interval. For sufficiently small BLT (e.g., BLT · 0:02), the CU approximation can provide an adequate starting point for analysis and design of DU loops. When BLT is increased in this approximation to larger, high-gain values, however, loop roots move away from their initial small-BLT damping and the loop diverges from expected behavior. Furthermore, actual loop noise bandwidth increases more rapidly
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